Monthly Archives: August 2015

OSI 300 Trainer

OSI-300 Mini Assembly

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Assembly of the OSI-300 Mini is fairly straightforward.  I typically start with the shortest height parts, and work up to the tallest.

  1. 1N4148/1N914 diodes D1-D20, D41, D42, and D43
    The black bar on each diode matches the bar on the silkscreen.
  2. 220 ohm resistors R1-R32, R35, and R39
  3. Remaining resistors:
    1. 4.7K ohm resistor R33
    2. 100K ohm resistor R34
    3. 100 ohm resistor R36
    4. 2.2K ohm resistor R37
    5. 4.7K ohm resistor R38
  4. 1N4001 diode D44
  5. .1uF capacitors C1-C5, C7-C9 (Lead spacing: 2.54mm/.1in)
  6. 10pF capacitor C6 (Lead spacing: 5.08mm/.2in)
  7. Sockets (five 14-pin, one 40-pin, one 28-pin)
  8. 3mm LEDs
    The flat edge matches the flat edge on the silkscreen.
  9. Switches
    There are two single-pole double-throw switches wich are different. They are to be used for the run and reset switches. They can be identified by the two slots on the side of the switch body.
  10. Single pin headers
    These should be broken out of the 6-pin breakable header
  11. Jumper
    I usually take a cut lead and bend it into a jumper to bridge the two pads above R34
  12. IC installation
    1. 7417N U1-U4 (buffers)
    2. 6502 U5 (CPU)
    3. 6264 U6 (SRAM)
    4. 7402 U7 (output)
  13. Rubber Feet
    I included two rubber feet to be placed under the OSI-300 Mini. They are too big to fit as-is, but can be cut with a sharp pair of scissors to form four half-circles.

A schematic of the PCB board can be found atminitrainer.pdf

I have found that I can test the board without the CPU and SRAM to ensure that the switches work properly by turning off/on the LEDs with the RUN switch set left.

The operation of the board can be accomplished by following the manual at Dave’s OSI repository

I’ve found that while programming, it is necessary to ensure that the RUN is left and RST is right. To run the program, switch RST left, then right, then switch RUN right, followed by RST to the left.  This sequence ensures that the clock starts properly.

Paul has also pointed out that the reset address used in the OSI manual needs to be adjusted due to the extra address lines.  In place of 7C and 7D, you will want to use FFC and FFD.

Update: at this point due to issues with the postal system I no longer will be mailing kits.  If this changes, I will update this post.

Tandy WP-2

Dumping the WP-2 ROM

As part of my project to run Zork on the Tandy WP-2, I found it useful to dump the ROM and take a peek at what it was doing.  While the Service Manual (available online from Club 100, the Internet Archive, and other places) contains a wealth of information, the code is the definitive place to look for information on how something works.

In order to dump the contents of the ROM, I wrote the below to read each code page, and write it out the serial port.  I compiled it with z80asm from Udo Munk’s z80pack.  I loaded the resulting binary onto the WP-2 by using a drive emulator (dlplus on Linux) and captured the results from the serial port to a file.  I then used an old version of IDA which supported the Z80 to perform the disassembly.

Combining the entry points from the service manual with the disassembly I could follow the code to answer questions regarding the operation of the WP-2 that were not completely clear from the manual.

; dumps all of the ROM banks to the serial port
; sets the serial port to 9600
; compile with z80asm -fb -vl DUMPROM.CO
CHARSENSE	equ		100H
CHARGET		equ		103H

SETLOC		equ		109H
GETLOC		equ		10CH
CURSORON	equ		10FH
CURSORTYPE	equ		112H

CHAROUT		equ		118h
PUTCHAR         equ		1A3H
STROUT		equ		11BH
CLS		equ		11EH
BEEP		equ		121H

RSINIT		equ		140H
GETDATALEN	equ		143H
SENDDATA	equ		146H
GETDATA		equ		149H
RSCLOSE		equ		14CH

CHGSLOT		equ		166H

LINEIN		equ		1A6H

BKSP		equ		008H
LF		equ		00AH
CR		equ		00DH
ESC		equ		01BH

		ORG		0AC00H-8
		DEFB		'PR'
		DEFW		PRGEND-PRGTOP+1
		DEFW		START
		DEFW		0000H

PRGTOP
START		CALL	CLS
		NOP
		NOP
		NOP
		NOP
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		NOP
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		NOP
		NOP
		NOP
		NOP
		NOP
		NOP
		XOR	A
		ld	(CURSLOT),a
		CALL	CHGSLOT		; change to slot zero to start
		ld	hl,0h		; start at zero to read the first bank
		ld	(current),hl
		call	DUMPLOOP
MAINLOOP:
		call	BEEP		; We dumped another block
		ld	hl,4000h	; remaining banks start at 4000h
		ld	(current),hl
		ld	a,(curslot)
		inc	a
		ld	(curslot),a	; bump to next slot
		cp	0Fh		; if slot 15 (IC Card)
		jr	z,DONE		; then we are done
		call	CHGSLOT
		call	DUMPLOOP	; otherwise dump it
		jr	MAINLOOP
DONE:		xor	a
		CALL	CHGSLOT		; change back to slot zero
		xor	a
		ret

DUMPLOOP:	
		ld	hl,084Dh	; 9600 bps, 8n1, no xon, timer enabled
		call	RSINIT
BYTELOOP:
		ld	hl,(current)
		ld	a,(hl)
		inc	hl
		ld	(current),hl
		call	SENDDATA
		ld	a,h
		cp	080h
		jr	nz,BYTELOOP
		call	SENDDATA	; for some reason we have to send
					; another dummy byte before the close
		call	RSCLOSE
		ret

CURRENT		DEFW	00000H
CURSLOT		DEFB	0h
PRGEND

		END